For a given node technology, increasing integrated circuit (IC) size typically increases the functionality that can be included on a chip. Unfortunately, defects often scale with chip area. A large chip is more likely to incorporate a defect than is a smaller chip. Defects affect yield, and yield loss often increases with increasing chip size. Various techniques have been developed to provide large ICs at desirable yield levels.
One approach to providing large ICs is to construct a large IC out of multiple smaller ICs (dice) on a silicon interposer. The silicon interposer is essentially a substrate that the dice are flip-chip bonded to after the silicon interposer has been processed to provide metal wiring and contacts. For example, a silicon wafer is fabricated to form one or more silicon interposers with several patterned metal layers and intervening insulating layers connected to vias, as are commonly called “back-end processing”. Conventional conductive vias through the insulating layers connect the patterned metal layers together, and the dice are physically and electrically connected to the interposer with micro-bump arrays.
These patterned metal layers provide a high density interconnect pattern to the IC dice. A silicon interposer typically connects the fine-pitched dice to a coarser bump array on the opposite side of the interposer, which is then connected to a printed circuit board or package substrate. An interposer can also provide inter-chip and intra-chip connections, such as by connecting several ground pins of one or more chips on the interposer to a common ground of the interposer. Conductive through-silicon vias (TSVs) extend through the silicon interposer to electrically connect the patterned metal layers of the interposer to the opposite side of the silicon interposer, typically as a bump array.
The topside of the interposer often has tens of thousands of fine-pitch microbumps that will be flip-chip bonded to corresponding microbump arrays of the ICs bonded to the interposer. Direct testing of finished interposers is difficult because the closeness of the topside contacts makes them very difficult to probe. Detecting TSV failures after IC chip mounting is undesirable because of the added component and fabrication costs that are lost if a composite IC fails due to TSV failure.
Providing techniques for insuring TSV yield that avoid the disadvantages of the prior art are desirable.